About this role
YOU…
verify mixed-signal designs on block and system level resting upon formal and functional verificationinterpret product requirements to create the verification concept and the product verification specificationperform random-constraint testbenches according to the state of the artcreate assertions to prove the design using formal methodswork in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites YOU…
have completed engineering degree in electrical engineering, computer science or similar studiesalready have practical experience in the field of digital functional verification and common safety standardshave extensive programming skills in coding in System Verilog and System Verilog assertionshave good knowledge of UVM methodology and Specman - e language, scripting languages like Python or Perl and ability to interpret RTL and Gatelevel codehave good communication skills in EnglishWe value diversity and therefore welcome all applications - regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity.
Severely disabled persons will be given preferential consideration if they are equally qualified.
Do you have any questions?
Then contact me: Özlem Mumin (Tel.: +49 89 255552-331)
Or apply now using our online application form.
Talent Management - we develop your careerWork life balance - flexible working hours and mobile working possibleFit and relaxed – with EGYM WellpassEnjoy biking – always on tour with bike leasingGreen Mobility - with us you can travel at a reduced rate...in addition we offer a permanent employment contract, corporate benefits and team events.