About this role
CPU Power-Management Design Engineer at Sifive. Location: Santa Clara or Cambridge or Austin or Boston. Role: designing clocking, defining PMU, verifying designs Requirements: 3+ years in CPU/SoC clocking, reset, power-management; Verilog/SystemVerilog; BS/MS in EE/CE/CS; AMBA knowledge; hardware verification experience. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, VHDL, Spyglass Commitment: Full Time Workplace: Onsite Languages: English