About this role
SoC Design Engineer at FuriosaAI. Location: Seoul, Seoul, Korea. Role: Integrate IP, Verify IP, Define specs Requirements: Master's degree in Electrical Engineering, Computer Science or equivalent; 2+ years in chip design; RTL design, logic synthesis, verification, timing closure Category: Engineering Seniority: Mid Level Tools: RTL design, logic synthesis, verification, timing analysis, FPGA, PCIe, USB, MIPI, simulation Commitment: Full Time Workplace: Onsite Languages: English