About this role
Sr. ASIC Design Engineer at Ambarella. Location: US Headquarters, United States. Role: Designing video compression, Implementing image processing, Developing test environments Requirements: Master’s degree in electrical/Electronics/Computer Engineering with 0-5 years of experience; knowledge of System Verilog, Verilog, python, and Perl; strong communication skills. Category: Engineering Seniority: Senior Level Tools: System Verilog, Verilog, Python, Perl Commitment: Full Time Workplace: Onsite Languages: English