About this role
Verification Engineer II at Ambarella. Location: United States. Role: Develop testbenches, Create test plans, Debug verification Requirements: Master’s degree in Electrical or Computer Engineering; strong SystemVerilog/UVM; digital design and SoC knowledge; C/C++, scripting (Python, Perl); experience with coverage. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, Verilog, C/C++, Python, Perl, CAD tools Commitment: Full Time Workplace: Onsite Languages: English