About this role
Verification Engineer at Altera. Location: New Delhi or Bengaluru. Role: verify designs, develop testbenches, execute regressions Requirements: Bachelor's or Master's in Electrical/Computer Engineering; 3+ years ASIC/FPGA verification; UVM SystemVerilog; HDL (Verilog/VHDL); CDV/ABV; scripting (Python/Perl/Tcl). Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, HDL Verilog, HDL VHDL, SystemVerification, Formal verification, AMBA PCIe Ethernet, Python, Perl, Tcl Commitment: Full Time Workplace: Remote Languages: English