About this role
Verification Engineer at Celero Communications, Inc.. Location: Ottawa, Ontario, Canada. Role: Develop verification, Design testbenches, Debug issues Requirements: 3+ years ASIC verification; Bachelor’s in Electrical/Computer Engineering or related; Verilog/SystemVerilog/UVM; MATLAB/C++; low-power design; strong problem-solving and teamwork. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, UVM, MATLAB, C, C++, Python, Tcl, Perl Commitment: Full Time Workplace: Onsite Languages: English