About this role
ASIC RTL/SoC Design Engineer at TETRAMEM INC. Location: Fremont, California, United States. Role: Lead RTL, Integrate IP, Collaborate with backend Requirements: MS with 5+ years or PhD in Electrical Engineering; Verilog/SystemVerilog; VCS/Verdi; pre/post-layout simulation; AMBA APB/AXI; ARM core architectures; leadership in design. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, VCS, Verdi, AMBA APB, AXI, ARM Commitment: Full Time Workplace: Onsite Languages: English, Telugu