About this role
ASIC Timing Engineer at Etched. Location: Cupertino, California, United States. Role: Drive timing, Collaborate design, Converge timing Requirements: BS or MS in Electrical/Computer Engineering; 5+ years timing/STA experience; full-chip timing analysis; ECOs; RTL-to-netlist; timing convergence; block/cluster/SoC validation. Category: Engineering Seniority: Senior Level Tools: STA, Fishtail, Lint, CDC, RDC, RTL to Netlist, Timing Constraints, ECOs Commitment: Full Time Workplace: Onsite Languages: English