About this role
Digital Design Engineer (Mid-Senior Level) at Movandi. Location: Riyadh, Riyadh, Saudi Arabia. Role: RTL ownership, Verification leadership, Timing closure Requirements: 5–10 years in digital IC/FPGA design; strong SystemVerilog/VHDL; RTL and verification expertise; timing closure; scripting in Python/Tcl; collaboration with hardware and software teams. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, VHDL, Verilog, Xilinx Vivado, Lattice Radiant, Cadence Genus, Cadence Innovus, Cadence Xcelium, cocotb, Python, Tcl, Git, Jenkins, Linux shell, Jira, GitHub Commitment: Full Time Workplace: Onsite Languages: English