About this role
ASIC / Physical Design Engineer at DiffLogic Inc.. Location: Santa Clara, California, United States. Role: design RTL, analyze timing, sign off Requirements: Experience with RTL-to-GDSII flow, synthesis, P&R, power and timing analysis, signoff, foundry waivers, and handoff; proficient in Synopsys and Cadence tools. Category: Engineering Seniority: Mid Level Tools: Synopsys tools, Cadence tools, RTL-to-GDSII, Synthesis, Placement and Routing, Power and Timing Analysis, DRC/LVS Commitment: Full Time Workplace: Onsite Languages: English