About this role
Senior FPGA Engineer at DRW. Location: Tel Aviv, Tel Aviv District, Israel. Role: Architect FPGA, Research FPGA, Liaise software Requirements: Bachelor’s in Computer or Electrical Engineering; 3+ years hardware/FPGA experience; strong RTL Verilog; capable of leading FPGA projects; proficient with FPGA design flow. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, FPGA design tools, Xilinx, Altera, Synthesis, Place & Route, Static timing analysis, SOC architectures, TCP/IP Commitment: Full Time Workplace: Onsite Languages: English