About this role
FPGA Engineer at Optiver. Location: Amsterdam, North Holland, Netherlands. Role: Design FPGA, Code RTL, Verify design Requirements: Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field; extensive FPGA/ASIC design experience; proficiency in VHDL, Verilog, SystemVerilog; RTL synthesis; digital simulators; post-silicon bring-up; collaboration with software teams. Category: Engineering Seniority: Senior Level Tools: VHDL, Verilog, SystemVerilog, RTL synthesis, C, C++, FPGA, ASIC Commitment: Full Time Workplace: Onsite Languages: English