About this role
ASIC Design Verification Engineer at Current Openings. Location: United States. Role: Develop verification, Lead environments, Collaborate teams Requirements: 8+ years ASIC verification; degree in EE/CE; SystemVerilog UVM; testbenches and coverage-driven verification; experience with EDA tools; scripting (Python/Perl/TCL). Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Simulation tools, Cadence tools, Synopsys tools, Mentor Graphics tools, Python, Perl, TCL Commitment: Full Time Workplace: Remote Languages: English