About this role
Senior FPGA Engineer at Oxford Quantum Circuits. Location: Reading, England, United Kingdom. Role: Define architecture, Design RTL, Develop interfaces Requirements: Senior FPGA Engineer with SystemVerilog/VHDL/Verilog expertise, timing closure, RTL design, high-speed data interfaces, DSP, and cross-disciplinary collaboration. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, VHDL, Verilog, Quartus, MATLAB/Simulink, Oscilloscopes, Spectrum Analyzers, DSP Commitment: Full Time Workplace: Hybrid Languages: English