About this role
Senior FPGA Engineer at Kayhut. Location: Israel. Role: defining requirements, designing RTL, running synthesis Requirements: Bachelor's or Master's in engineering; 3+ years FPGA design flow experience; strong RTL design/verification (Verilog/VHDL/System Verilog); XILINX/VIVADO experience; timing, clocking, CDC knowledge; problem-solving and teamwork skills. Category: Engineering Seniority: Mid Level Tools: System Verilog, Verilog, VHDL, XILINX, VIVADO, Python, C, C++, MATLAB, logic analyzers, oscilloscopes, FPGA toolchains Commitment: Full Time Workplace: Onsite Languages: English