About this role
Senior FPGA Engineer at Advanced Navigation. Location: Sydney, New South Wales, Australia. Role: designing FPGA, debugging defects, documenting specifications Requirements: Bachelor-level engineering, 8+ years commercial FPGA development experience, expertise in VHDL/Verilog, Vivado and Quartus toolchains, timing closure and CDC, hardware debug (ChipScope/ILA, SignalTap), high-speed interfaces knowledge, and C for embedded software. Category: Engineering Seniority: Senior Level Tools: Vivado, Quartus, VHDL, Verilog, SDC, XDC, ChipScope, ILA, SignalTap, C, C++, Python, MATLAB, Bash, UVVM, OSVVM, UVM Commitment: Full Time Workplace: Onsite Languages: English