About this role
Interconnect Design Engineer at Sifive. Location: Santa Clara or Cambridge or Austin or Boston. Role: designing interconnect, implementing generators, performing verification Requirements: Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent. Category: Engineering Seniority: Senior Level Tools: Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence Commitment: Full Time Workplace: Onsite Languages: English