About this role
Verification Engineer at Quantum Machines. Location: Tel Aviv-Yafo, Tel Aviv District, Israel. Role: creating environment, integrating vip, defining verification Requirements: 3+ years verification experience; must have UVM and System Verilog; experience with VIP/protocols (PCIe, DDR, AXI); able to build verification environments from scratch; C/C++/Python/System C and HW-SW knowledge are advantages. Category: Engineering Seniority: Mid Level Tools: UVM, System Verilog, Verification IPs, PCIe, DDR, AXI, C, C++, Python, System C Commitment: Full Time Workplace: Hybrid Languages: English