About this role
Senior Verification Engineer at Morse Micro. Location: Sydney, New South Wales, Australia. Role: architecting testbenches, debugging RTL, driving verification Requirements: 5+ years in pre-silicon ASIC verification (SystemVerilog/UVM/Formal); SV testbench development; COCOTB; embedded C; security IP verification; RTL debugging; coverage analysis. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Formal, COCOTB, Python, C, Verilator, AMBA, TileLink Commitment: Full Time Workplace: Onsite Languages: English