About this role
Lead RTL Design Engineer at Efficient Computer. Location: Austin or Pittsburgh or San Jose. Role: define microarchitecture, drive on-chip interconnects, design memory interface Requirements: 8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler Commitment: Full Time Workplace: Onsite Languages: English