About this role
Digital Verification Engineer at IMEC. Location: Leuven, Flemish Brabant, Belgium. Role: verifying blocks, debugging designs, documenting reports Requirements: MSc or PhD in electronics engineering with 5+ years experience; strong SystemVerilog/UVM verification skills; CPU/peripheral verification experience; verification planning, coverage, constrained-random, TCL/Python and git proficiency. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, TCL, Python, git, Cadence IC design tools Commitment: Full Time Workplace: Onsite Languages: English