About this role
Verification Engineer at NextSilicon. Location: Giv'atayim, Tel Aviv District, Israel. Role: reviewing specifications, designing testbenches, building environment Requirements: 6+ years verification experience, bachelor in electrical engineering or computer science, expertise in SystemVerilog/UVM/Spaceman and Verilog, strong knowledge of SOC architecture, constrained-random verification, and coverage methodologies. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Spaceman, Verilog, Verilog simulator Commitment: Full Time Workplace: Hybrid Languages: English