About this role
FPGA Engineer at Sateliot. Location: Barcelona, Catalonia, Spain. Role: Design RTL, Integrate IP, Verify design Requirements: Bachelor's or Master's in Electrical, Telecommunications, or Computer Engineering; 2-4 years FPGA design; SystemVerilog/VHDL; AXI; Linux; Python/Tcl; English; AI tooling experience. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, VHDL, AXI4, AXI4-Stream, AXI4-Lite, Vivado xsim, ModelSim, Questa, Linux, Git, Python, Tcl Commitment: Full Time Workplace: Hybrid Languages: English