About this role
Staff FPGA Engineer at Axiado. Location: Taipei, Taiwan, Taiwan. Role: test interfaces, design logic, integrate tooling Requirements: FPGA engineer with Verilog/SystemVerilog, SPI/eSPI/LTPI, I2C/I3C; FPGA design for Xilinx/Intel/Lattice; strong communication; BS/MS in EE or CE. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, Vivado, Xilinx FPGA, Intel FPGA, Lattice FPGA Commitment: Full Time Workplace: Onsite Languages: English