About this role
Staff Engineer, FPGA at Samsung Semiconductor. Location: San Jose, California, United States. Role: Design RTL, Manage queues, Ensure coherency Requirements: 10+ years FPGA/RTL design, BS in Electrical/Computer Engineering; 3-5+ years in high-performance FPGA; strong SystemVerilog/Verilog; experience with Xilinx Vivado/Intel Quartus; knowledge of AXI/AXIS, PCIe, CXL. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, Xilinx Vivado, Intel Quartus, Questa, Xcelium, VCS, PCIe, CXL.cache, AMBA AXI/AXIS, CXL Type-1/2 Commitment: Full Time Workplace: Onsite Languages: English