About this role
Senior/Staff Mid-End Engineer (STA/Synthesis) at Bitdeer Technologies Group. Location: Singapore or Ayer Itam. Role: performing synthesis, conducting STA, optimizing power Requirements: Bachelor's degree in EE/CE, 3+ years IC design experience focused on synthesis, timing closure, and power optimization; proficiency in Verilog/SystemVerilog, EDA tools, STA, and scripting (TCL/Python/Perl/Shell). Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus, Conformal, FormalPro, JasperGold, TCL, Python, Perl, Shell Commitment: Full Time Workplace: Onsite Languages: English