About this role
Junior FPGA Developer at Edgehog Trading. Location: Chicago, Illinois, United States. Role: designing RTL, developing testbenches, running synthesis Requirements: BS/MS in EE/CE or related field, hands-on RTL design in Verilog/SystemVerilog, familiarity with ModelSim/QuestaSim/Vivado/Quartus and synthesis flow, Linux proficiency, Python/C/C++ a plus, eagerness to apply AI tools and learn HFT. Category: Engineering Seniority: Entry Level Tools: Verilog, SystemVerilog, ModelSim, QuestaSim, Vivado, Quartus, Linux, Python, C, C++ Commitment: Full Time Workplace: Onsite Languages: English