About this role
SoC Design Director at Astera Labs. Location: Bengaluru, Karnataka, India. Role: designing solutions, developing RTL, overseeing debug Requirements: 12+ years digital design experience with RTL, SystemVerilog/Verilog, synthesis, timing closure, PCIe, processor IP (ARM/ARC), UVM verification, Synopsys/Cadence tools, silicon bring-up, and scripting (Python/Perl). Bachelor's in Electronics/Electrical engineering required. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, Python, Perl, Synopsys, Cadence, UVM Commitment: Full Time Workplace: Onsite Languages: English