About this role
Staff ASIC Design Engineer at Ambarella. Location: United States. Role: designing systems, implementing logic, optimizing rtl Requirements: Master's in electrical/electronics/computer engineering, 5+ years VLSI experience with computer architecture, System Verilog/Verilog, Python/Perl scripting, RTL synthesis and verification, assembly programming, and strong communication skills. Category: Engineering Seniority: Senior Level Tools: System Verilog, Verilog, Python, Perl Commitment: Full Time Workplace: Onsite Languages: English