About this role
Senior Engineer (Level 1) at Arrow. Location: Bangalore, Karnataka, India. Role: designing asics, coding logic, verifying designs Requirements: ASIC design lifecycle experience including design, development, simulation, test, debug, verification; coding in Verilog, VHDL, System Verilog; typically requires a 4-year degree and ~5+ years related experience (or equivalent). Category: Engineering Seniority: Senior Level Tools: Verilog, VHDL, System Verilog Commitment: Full Time Workplace: Onsite Languages: English