About this role
Principal Digital Design Engineer at PowerLattice. Location: Chandler or Vancouver or Remote. Role: Define microarchitecture, Lead RTL design, Integrate blocks Requirements: Bachelor's or master's in electrical/computer engineering; 10+ years in digital design with RTL; SoC/subsystem tapeout experience; strong RTL, microarchitecture, back-end flows, DFT/scan, LEC, STA, SDC skills; solid timing, power, and debug expertise. Category: Engineering Seniority: Senior Level Tools: Synopsys, Cadence, EDA tools, Synthesis, DFT, LEC, STA, SDC, UPF/CPF, RTL Commitment: Full Time Workplace: Hybrid Languages: English