About this role
Advanced IC Packaging Engineer at Powerlattice Technologies Inc.. Location: Chandler, Arizona, United States. Role: developing packaging, integrating chiplets, analyzing data Requirements: MS/PhD preferred in EE/Materials/Mechanical, 8+ years semiconductor packaging experience (2.5D/3D, chiplets, substrate integration), DoE and statistical analysis experience, failure analysis and solder/interconnect expertise. Category: Engineering Seniority: Senior Level Commitment: Full Time Workplace: Hybrid Languages: English