About this role
Principal Interconnect Design Engineer at Sifive. Location: Santa Clara or Cambridge or Austin or Boston. Role: designing interconnect, implementing generators, integrating ip Requirements: Expertise in interconnects, cache/coherency, NoC and bus protocols (AXI, AHB, APB, CHI, CXL, UCIe); RTL design in Verilog/SystemVerilog/VHDL; experience with Chisel/FIRRTL/Scala preferred; BS/MS in EE/CE/CS or equivalent. Category: Engineering Seniority: Senior Level Tools: Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Git, GitHub, Jira, Confluence Commitment: Full Time Workplace: Onsite Languages: English