About this role
Interconnect Design Engineer at SiFive. Location: Santa Clara or Cambridge or Austin or Boston. Role: designing interconnect, implementing generators, integrating framework Requirements: Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred). Category: Engineering Seniority: Senior Level Tools: Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence Commitment: Full Time Workplace: Onsite Languages: English