Senior Staff Design Verification Engineer – Coherent Interconnect @ Sifive

Senior Staff Design Verification Engineer – Coherent Interconnect at Sifive. Location: Boston or Austin. Role: owning verification, developing environments, debugging failures Requirements: 8+ years ASIC/SoC design verification experience; strong SystemVerilog and Python skills; deep understanding of cache-coherent interconnects, protocols (CHI/ACE/CXL/AXI), test plans, assertions, and coverage models; BS/MS in EE/CE/CS required. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Python Commitment: Full Time Workplace: Onsite Languages: English