Senior Staff Design Verification Engineer – Coherent Interconnect @ Sifive

Senior Staff Design Verification Engineer – Coherent Interconnect at Sifive. Location: Boston or Austin. Role: defining strategy, developing environments, mentoring engineers Requirements: 8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Python Commitment: Full Time Workplace: Onsite Languages: English