About this role
Physical Design Engineer at Intel. Location: Bangalore, Karnataka, India. Role: owning design, running flows, improving QoR Requirements: Hands-on block-level physical design experience (RTL→GDSII) with Synopsys/Cadence tools, physical verification (ICV), TCL/Python scripting, and 5+ years of relevant VLSI physical design experience. Category: Engineering Seniority: Senior Level Tools: Synopsys, Cadence, Fusion Compiler, Innovus, ICV, TCL, Python Commitment: Full Time Workplace: Hybrid Languages: English