About this role
DV - Verification Engineer - AMS modeling at Eliyan. Location: Vancouver or Toronto. Role: Develop RNM, Verify models, Collaborate design Requirements: BS in EE or related field; experience with analog/mixed-signal verification; SystemVerilog, UVM; RNM AMS modeling; scripted testing. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, Jasper Gold, vc-formal, Python, Perl, Tcl Commitment: Full Time Workplace: Onsite Languages: English