About this role
Senior Analog IC Design Engineer (f/m/d) at Renesas Design Zurich AG. Location: Zurich, Zurich, Switzerland. Role: designing circuits, simulating designs, supporting validation Requirements: M.S. or Ph.D. in Electrical Engineering, minimum 2 years analog IC design experience, CMOS analog fundamentals, power-management analog block design, Cadence Virtuoso and Spectre experience, strong analytical and teamwork skills. Category: Engineering Seniority: Entry Level Tools: Cadence Virtuoso, Spectre, Python, SKILL, Perl, Tcl Commitment: Full Time Workplace: Onsite Languages: English