About this role
PCB Layout Engineer Intern (Fall 2026) at Astranis. Location: San Francisco, California, United States. Role: placing PCBs, routing PCBs, creating footprints Requirements: Currently enrolled EE student; familiar with Altium/ECAD; basic analog, RF, power and digital electronics knowledge; US citizen or lawful permanent resident required. Category: Engineering Seniority: Entry Level Tools: Altium, ECAD, PLM Commitment: Internship Workplace: Onsite Languages: English