About this role
Senior Principal SOC Design Engineer at MaxLinear. Location: Singapore. Role: coding RTL, developing microarchitecture, collaborating cross-functionally Requirements: Bachelor's or Master's in Electronics Engineering and 18+ years' experience. Expert VHDL/Verilog RTL coding, front-end SoC integration, IP development, verification skills, linting tools (Spyglass, Real Intent), IP-XACT, C/C++, assembly, SVA, and ARM/AXI/AHB/NoC experience. Category: Engineering Seniority: Senior Level Tools: VHDL, Verilog, Spyglass, Real Intent, IP-XACT, C, C++, assembly, SVA, ARM, AXI, AHB, SERDES, UART, I2C, SPI, NoC, DDR, RTL, DfT Commitment: Full Time Workplace: Onsite Languages: English