About this role
<p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt"><strong><span style="font-family:Verdana, sans-serif;color:black">Job Title: Sr. Specialist, Systems Engineer (Systems/Software)</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt"><strong><span style="font-family:Verdana, sans-serif;color:black">Job Code: 40367</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt"><strong><span style="font-family:Verdana, sans-serif;color:black">Job Location:</span></strong><strong><span style="font-family:Verdana, sans-serif"> Camden, NJ (on-site)</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt"><strong><span style="font-family:Verdana, sans-serif">Schedule: 9/80 Regular Schedule (</span></strong></span><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif"> 9/80 Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off</span><span style="font-size:14.0pt"><strong><span style="font-family:Verdana, sans-serif"> )</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="line-height:105%;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:12.0pt;line-height:105%;font-family:Verdana, sans-serif"> </span></strong></p> <p style="line-height:105%;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-size:12.0pt;line-height:105%;font-family:Verdana, sans-serif;color:black">L3Harris is dedicated to recruiting and developing diverse, high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do.</span></em></p> <p style="line-height:105%;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-size:12.0pt;line-height:105%;font-family:Verdana, sans-serif;color:black"> </span></em></p> <p style="line-height:105%;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><em><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">About L3Harris Technologies – Maritime Power Systems:</span></em></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">L3Harris Technologies Power Systems is an agile defense technology innovator, delivering end-to-end solutions for the US Navy Shipbuilding programs. With capabilities in ship control systems, manufacturing and turn-key ship overhauls that meet customers’ mission-critical needs.</span></em></p> <p style="line-height:105%;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-size:12.0pt;line-height:105%;font-family:Verdana, sans-serif;color:black"> </span></em></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif">JOB DESCRIPTION:</span></strong></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif"> </span></strong></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">This <strong>Systems Software Engineer</strong> will be responsible for designing, building and delivering a wide range of safety critical, cybersecure power solutions to military customers. Leading or participation in all stages of the systems/software development life cycle (SDLC).</span></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">The <strong>System Engineering portion</strong> of this role is to ensure the final system meets or exceeds all customer system requirements. The systems portion of this role involves working closely with electrical, mechanical, software and test engineers to capture system requirements and develop traceable contract SDRL documentation, customer specifications and operators’ manuals when required. Also work with Program Managers and Project Engineers to develop proposals, project schedules and participate in customer reviews of design and test artifacts.</span></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">The <strong>Software Engineering portion </strong>of this role involves designing, developing, testing, and maintaining software applications and systems. For most products this involves formal software design and test documentation traceable to system requirements. PS software products require high reliability, safety critical, and cybersecure software operation with built in test features for mission critical power systems and switchgear. Coding effort can span from low level embedded DSP or ARM based controllers previously written in ASM/C/C++ to coding for Human Machine Interface (GUI design) in C# or other GUI based language. </span></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">IRAD Development may include hardware and software prototypes for proof-of-concept efforts involving the design and test of new embedded software with built in test features for integration with hardware and support for final qualification testing. </span></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Essential Functions:</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Lead and represent the organization on technical aspects of assigned projects, including peer reviews and resolution of difficult technical issues. </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Coordinate system level requirements internally and among subcontractors and suppliers.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Support evaluating, planning, and estimation of tasks.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Generate design review materials and communicate design decisions.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Adhere to budget and schedule commitments.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Capable of providing technical supervision and training/mentoring to lower-level engineers.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Develop subsystem architecture artifacts, including block diagrams, functional allocations, interfaces, and timing diagrams.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Prepare system and subsystem level specifications.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Generate Test Plans for systems and subsystems to ensure validation of requirements.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Creation of Documentation in accordance with internal and/or customer standards.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Risk identification and migration planning.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Trade-off analysis and strategy.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Represents organization in providing solutions to difficult technical issues associated with specific projects.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif">Develop, maintain, and continuously improve Systems Engineering design, validation, and qualification processes<span style="color:black">. </span></span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Comfortable working in a multi-disciplined engineering group to achieve results.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Ability to handle multiple tasks in a fast-paced, constantly changing environment. </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Ability to work both independently and as part of a team.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Travel up to ~10% as needed.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Ability to obtain and maintain a US Security Clearance.</span></li> </ul> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Qualifications:</span></strong></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Bachelors and minimum 6 years prior experience or Master’s Degree with a minimum of 4 years’ experience in Systems Engineering, Computer Engineering, Electrical Engineering, Mechanical Engineering, or related field.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">At least 4 years of experience with systems engineering background, and knowledge of lifecycle and standards.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with system engineering principles including requirements writing, modeling, and verification testing. </span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with C programming and familiarity with Assembly. </span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience writing systems and software test procedures.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Knowledge of systems utilizing embedded software. Up to date on current Systems Engineering trends, technology, and tools (including DOORS and JIRA). </span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Proven track record of working through customer requirements to technical requirements to product solutions.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience reading PCB designs.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Working knowledge of standard system engineering processes such as: MIL-STD-499, EIA-632, IEEE 1220 or ISO 15288.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Technical writing experience, including experience generating and presenting technical documents to internal and external customers. </span></li> </ul> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Preferred Additional Skills:</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Active Secret clearance.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience overseeing the systems/software development life cycle (SDLC).</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with development of high-power electrical devices and interfaces </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with PCB development and test jigs and test utilities for production</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with administering projects using Atlassian JIRA, Confluence, Bitbucket </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with embedded processors including ARM, INTEL, TI TMS320 DSP micros </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with JTAG/ICE programming and build versus runtime software image verification methods (CRC, HASH128,256…)</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with various code development tools:</span> <ul style="list-style-type:circle;margin-top:0.0in;margin-bottom:0.0in"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Visual Studio IDE</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Texas Instruments Code Composer Studio IDE</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Python IDE</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Keil uVision IDE </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Intel Quartis FPGA IDE</span></li> </ul> </li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience administering Software and Systems configuration management Server:</span> <ul style="list-style-type:circle;margin-top:0.0in;margin-bottom:0.0in"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Atlassian Jira, Fisheye and Crucible Server and Clients management</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">SVN Server and Clients management</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">PostGRE SQL database</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">IBM DOORs </span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">GIT and BitBucket</span></li> </ul> </li> <li style="margin:0.0in 0.0in 8.0pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Strong ability to communicate at different levels depending upon target audience. Examples include technical presentations to current customers as well as defense of proposals for future business. </span></li> </ul> <p style="line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif;margin:0.0in 0.0in 0.0in 0.0px"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in 0.0in 0.0in 0.5in;font-size:11.0pt;font-family:Calibri, sans-serif">In compliance with pay transparency requirements, the salary range for this role is $106,500 - $197,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.</p> <p style="margin:0.0in 0.0in 0.0in 0.5in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in 0.0in 0.0in 0.5in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="color:white;background-color:white">#LI-IK1</span></p>