About this role
Microchip Technology FPGA Business group is seeking a highly skilled and experienced System Interconnect Architect to join our dynamic team. The successful candidate will be responsible for leading cross-functional teams to deliver high-performance IP integrations into our FPGA products, that meet market & customer requirements across a broad range of application spaces.
This position is in the Silicon Architecture team of Microchip’s FPGA Division. Microchip is a major supplier of low-power and highly-reliable field-programmable gate arrays (FPGAs). Our FPGAs are used in a wide variety of applications, including embedded vision; digital signal processing; machine learning; industrial and medical equipment; and satellites. Microchip is also a pioneer in embedding RISC-V processors in FPGAs.
The successful applicant will work as part a core team to develop future FPGA device products and will collaborate with other engineering disciplines to model, develop, verify, and integrate System Interconnect components such as IO, hard IP blocks, hard & soft IP solutions, that interoperate with overall configuration and security features to deliver performant FPGA products.
Key Responsibilities:
Lead cross-functional teams to deliver high-performance IP integrations into Microchip FPGA products
Work on ASIC & FPGA IP development, integration, and deployment for System Interconnect such as PCIe, CXL, DDR, NOC, High Speed Serial Transceivers, High Performance Parallel IO interfaces
Understand customer use models and the role of IP in overall system architecture
Work cross-functionally with other architects, designers, and back-end implementation teams
Lead and manage other engineers in the team
MS or higher in EE, CS, CE or other applicable disciplines
12+ years of relevant experience
Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floor planning, timing closure, CDC/RDC
Knowledge and experience with system-level performance modeling in TLM/SystemC/Other will be an advantage
Experience in technical leadership and people management will be an advantage
Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams
Knowledge and experience with Synopsys & Cadence ASIC flows
Scripting for EDA in Perl, Python, Tcl will be an advantage
Travel Time:
0% - 25%
Physical Attributes:
Feeling, Handling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others
Physical Requirements:
10% walking, 10% standing, 80% sitting; 100% in doors; Usual business hours
Pay Range:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip
The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.*
*Range is dependent on numerous factors including job location, skills and experience.
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.