Job Title: Senior Specialist, Systems Engineering - FPGA & GPU Job Code: 39548 Job Location: Greenville, TX Job Schedule: 9/80 - Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off Job Description: Senior Specialist, Systems Engineer – FPGA/GPU & RF Signal Processing. The Senior Specialist, Systems Engineer will be responsible for the architectural design, development, and analysis of advanced FPGA and GPU‑based signal processing solutions supporting complex ISR sensor systems. The candidate will perform architectural design, coding, test bench development, and simulation activities, while also contributing to broader systems engineering tasks across RF, radar, DSP, and integration domains. This role supports development from concept through integration and delivery, requiring strong analytical skills, technical leadership, and cross-functional coordination. The candidate will set the highest ethical standards for self and others and perform other duties as assigned. Essential Functions: <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Lead FPGA/GPU architectural design, HDL coding, test bench creation, simulation, and analysis for high‑performance DSP and signal processing applications.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Perform RF, microwave, and radar‑related analysis including spectrum behavior, propagation effects, receiver/front‑end characteristics, pulse parameters, PRI/PW/RF measurement, modulation recognition, and emitter characterization.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Apply DSP techniques including FFTs, filtering, detection, estimation, and time‑frequency analysis to support system design and verification.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Execute systems engineering tasks including requirements development (JIRA/DOORS), CONOPS definition, integration planning, test procedures, and performance analysis.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work closely with cross-functional engineering teams to plan and conduct system integration testing in laboratory and platform environments.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Document system behavior, anomalies, and integration results following established engineering standards; verify and validate system functionality across new and legacy baselines.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Support troubleshooting of RF chains, timing/synchronization issues, calibration, and hardware/software interaction during system integration.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Collaborate with customers to ensure satisfaction with system performance and to clarify operational requirements.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Provide technical updates to management and customers, contributing to schedule, risk, and resource planning.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Produce end-user documentation, integration reports, and technical analysis packages as required.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work effectively in a fast-paced environment with time‑critical program milestones and evolving technical objectives.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Active Secret or recently held Top Secret/SCI security clearance with the ability to maintain.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to work occasional overtime or weekend hours if required.</li> </ul> Qualifications: <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Bachelor’s Degree and minimum 6 years of prior relevant engineering experience.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Graduate Degree and a minimum of 4 years of prior related engineering experience.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In lieu of a degree, a minimum of 10 years of prior related engineering experience.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated experience with FPGA or GPU‑based design, including VHDL/Verilog/CUDA, test benches, and simulation tools.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated understanding of RF and microwave fundamentals, including antennas, receivers, spectral behavior, and front-end design.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated experience with signals analysis techniques and tools, including pulse analysis, modulation assessment, and emitter characterization.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated knowledge of radar fundamentals such as pulse radar, CW/FMCW, LPI principles, scan patterns, and threat system behavior.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated experience in MATLAB and Python for algorithm development, modeling, automation, data analysis, and visualization.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated experience working with large IQ/sample data sets and developing automated processing workflows.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated familiarity with test equipment including spectrum analyzers, signal generators, oscilloscopes, vector signal analyzers, and AWGs.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated experience with SDR platforms, digitizers, and receiver systems.</li> </ul> Preferred Additional Skills: <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Active TS/SCI.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with integration and troubleshooting of complex RF or electronic warfare receiver systems.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with JIRA, Confluence, and DOORS for requirements and workflow management.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with advanced DSP algorithm development and implementation.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with system‑level SEI, LPI/LPE techniques, or advanced emitter analysis methodologies.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience in software integration and system-level test.</li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Proficiency with standard office and documentation tools.</li> </ul> #LI-AM2

Senior Specialist, Systems Engineer - FPGA & GPU (Greenville, TX, US, 75402) @ L3Harris Technologies, Inc.

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