About this role
Senior/Staff Front-End Engineer (SOC) at Bitdeer Technologies Group. Location: Singapore or Malaysia. Role: implementing RTL, integrating IPs, supporting synthesis Requirements: Design and implement Verilog RTL for SoC, integrate IPs, support synthesis/timing/power/floorplanning, contribute to verification and emulation, debug pre- and post-silicon issues; scripting with Perl, Shell, TCL; 5+ years semiconductor experience preferred. Category: Engineering Seniority: Senior Level Tools: Verilog, Perl, Shell, TCL, FPGA Commitment: Full Time Workplace: Onsite Languages: English