About this role
Senior/Staff Front-End Engineer (CPU/Processor) at Bitdeer Technologies Group. Location: Singapore or Ayer Itam. Role: implementing RTL, ensuring coverage, debugging issues Requirements: Develop Verilog RTL for RISC-V CPUs, ensure verification coverage, support pre-/post-silicon debugging, collaborate with verification and software teams; scripting (Perl, Shell, TCL) and SoC/IP experience preferred. Category: Engineering Seniority: Senior Level Tools: Verilog, RISC-V, Perl, Shell, TCL Commitment: Full Time Workplace: Onsite Languages: English